Bulldozer (processor)

Bulldozer is the codename AMD has given to one of the next-generation CPU cores after the K10 microarchitecture for the company's M-SPACE design methodology, with the core specifically aimed at 10 watt to 100 watt TDP computing products. Bulldozer is a completely new design developed from the ground up. AMD claims dramatic performance-per-watt improvements in HPC applications with Bulldozer cores. Products implementing the Bulldozer core are planned for release in 2011.



According to AMD, Bulldozer-based CPUs will based on advanced 32nm SOI process technology and utilize a new approach to multithreaded compute performance that, according to press notes, "balances dedicated and shared compute resources to provide a highly compact, high core count design that is easily replicated on a chip for performance scaling." In other words, by eliminating some of the redundancies that naturally creep into multicore designs, AMD hopes to take better advantage of its hardware capabilities, while utilizing less power.

The Bulldozer cores will support most of the instruction sets currently implemented in Intel processors (including SSE4.1, SSE4.2, AES, CLMUL), future Instruction sets announced by Intel (AVX), as well as future instruction sets proposed by AMD (XOP and FMA4).

As of November 2009, Bulldozer-based implementations built on 32nm SOI with HKMG are scheduled to arrive in 2011 for both servers and desktops, as the 16-core Opteron processor codenamed Interlagos and as the 4- or 8-core desktop processor codenamed Zambezi.

Bulldozer is the next-generation micro-architecture and processor design developed from the ground up by AMD. Bulldozer will be the first major redesign of AMD’s processor architecture since 2003, when the firm launched its Athlon 64/Opteron (K8) processors. Bulldozer will feature two 128-bit FMA-capable FPUs which can be combined into one 256-bit FPU. This design is accompanied with two integer cores each with 4 pipelines (the fetch/decode stage is shared). Bulldozer will also introduce shared L2 cache in the new architecture. AMD calls this design a "Bulldozer module". A 16-core processor design would feature eight of these modules, but the operating system will see each module as two physical cores.

The module is similar to an SMT core, but enhanced with a dedicated integer core and scheduler for each thread. Because the shared floating point core is significantly enhanced, performance could get beyond that of two equivalent Bobcat cores while one of the running threads is integer-only.