Floating Junction Gate- FJG

FJG RAM, short for Floating Junction Gate Random Access Memory, is the newest type of computer memory so far invented by Oriental Semiconductor Co., Ltd. The FJG RAM offers ultra-compact cell area as small as 4F2 (F is the feature size); capacitorless cell configuration; high performance operation as well as simple process. Moreover, it requires neither exotic process steps or materials, nor new process tools. The process of making such a device is simply available from all existing DRAM fabs. Due to its capacitorless property, the FJG cell process is more compatible with logic process, enabling its great potential not only in the standalone DRAM application but also the embedded-DRAM applications. Other merits such as non-destructive-read; shared sense-amplifiers can help DRAM designers to reduce the complexity of the periphery circuits.



Basic Operation
The FJG device generally consists of one floating gate NMOS and one MOS gated diode. The floating gate NMOS has different threshold voltages at different logic states. By charging or discharging the floating gate via the current path through the gated diode, the threshold voltage of the floating gate NMOS is changed. Since the floating gate is connected to a p-n junction, this cell is called a "floating junction gate (FJG)" cell. When reading the cell, with the same voltage conditions on the control gate, the NMOS has different sense current at different logic states. The sense current can then be amplified by a sense amplifier. Thus, the state of the cell can be determined.

Electrical Characteristic

Program and Read Operations

Writing logic "1" and "0" is done by charging and discharging the floating gate in an FJG cell. It is done through current flowing through the pn diode under different voltage stress conditions at different contact nodes. When charging the floating gate, the pn diode is reverse biased, causing large band bending at the floating gate/channel junction. Band-to-Band tunneling will occur under such condition causing electrons tunnel from the floating gate to the channel(Fig.3(a)). Discharging the floating gate is realized by forward biasing the pn diode and draining the charges out of the floating gate(Fig.3(b)). Both processes can be done within a few nano seconds, which enables ultra high speed operation. Fig. 4 illustrates the transient characterization of the read and write operations of an FJG device, wherein the write logic "1" and "0" operations take 5 ns including 1ns rising/falling edge of the signal pulse. It can be seen that the read logic "1" current is as high as 20μA after the write logic "1" operation while the read logic "0" current is less than 1μA after the write "0" operation. The write "1" operation can be even faster with an increased VD-S.